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ad574aCspecifications ad574aj ad574ak ad574al model min typ max min typ max min typ max units resolution 12 12 12 bits linearity error @ +25 c 1 1/2 1/2 lsb t min to t max 1 1/2 1/2 lsb differential linearity error (minimum resolution for which no missing codes are guaranteed) t min to t max 11 12 12 bits unipolar offset (adjustable to zero) 2 1 1 lsb bipolar offset (adjustable to zero) 4 4 2 lsb full-scale calibration error (with fixed 50 w resistor from ref out to ref in) (adjustable to zero) 0.25 0.25 0.125 % of fs temperature range 0 +70 0 +70 0 +70 c temperature coefficients (using internal reference) t min to t max unipolar offset 2 (10) 1 (5) 1 (5) lsb (ppm/ c) bipolar offset 2 (10) 1 (5) 1 (5) lsb (ppm/ c) full-scale calibration 9 (50) 5 (27) 2 (10) lsb (ppm/ c) power supply rejection max change in full-scale calibration v cc = 15 v 1.5 v or 12 v 0.6 v 2 1 1 lsb v logic = 5 v 0.5 v 1/2 1/2 1/2 lsb v ee = C15 v 1.5 v or C12 v 0.6 v 2 1 1 lsb analog input input ranges bipolar C5 +5 C5 +5 C5 +5 volts C10 +10 C10 +10 C10 +10 volts unipolar 0 +10 0 +10 0 +10 volts 0 +20 0 +20 0 +20 volts input impedance 10 volt span 3 5 7 3 5 7 3 5 7 k w 20 volt span 6 10 14 6 10 14 6 10 14 k w digital characteristics 1 (t min Ct max ) inputs 2 (ce, cs , r/ c, a 0 ) logic 1 voltage +2.0 +5.5 +2.0 +5.5 +2.0 +5.5 volts logic 0 voltage C0.5 +0.8 C0.5 +0.8 C0.5 +0.8 volts current C20 +20 C20 +20 C20 +20 m a capacitance 5 5 5 pf output (db11Cdb0, sts) logic 1 voltage (i source 500 m a) +2.4 +2.4 +2.4 volts logic 0 voltage (i sink 1.6 ma) +0.4 +0.4 +0.4 volts leakage (db11Cdb0, high-z state) C20 +20 C20 +20 C20 +20 m a capacitance 5 5 5 pf power supplies operating range v logic +4.5 +5.5 +4.5 +5.5 +4.5 +5.5 volts v cc +11.4 +16.5 +11.4 +16.5 +11.4 +16.5 volts v ee C11.4 C16.5 C11.4 C16.5 C11.4 C16.5 volts operating current i logic 30 40 30 40 30 40 ma i cc 25 25 25ma i ee 18 30 18 30 18 30 ma power dissipation 390 725 390 725 390 725 mw internal reference voltage 9.98 10.0 10.02 9.98 10.0 10.02 9.99 10.0 10.01 volts output current (available for external loads) 3 1.5 1.5 1.5 ma (external load should not change during conversion) package options 4 ceramic (d-28) ad574asd ad574akd ad574ald plastic (n-28) ad574ajn ad574akn ad574aln plcc (p-28a) ad574ajp ad574akp lcc (e-28a) ad574aje ad574ake notes 1 detailed timing specifications appear in the timing section. 2 12/ 8 input is not ttl-compatible and must be hard wired to v logic or digital common. 3 the reference should be buffered for operation on 12 v supplies. 4 d = ceramic dip; n = plastic dip; p = plastic leaded chip carrier. specifications subject to change without notice. (@ +25 8 c with v cc = +15 v or +12 v, v logic = +5 v, v ee = C15 v or C12 v unless otherwise noted) rev. b C2C
ad574as ad574at ad574au model min typ max min typ max min typ max units resolution 12 12 12 bits linearity error @ +25 c 1 1/2 1/2 lsb t min to t max 1 1 1 lsb differential linearity error (minimum resolution for which no missing codes are guaranteed) t min to t max 11 12 12 bits unipolar offset (adjustable to zero) 2 1 1 lsb bipolar offset (adjustable to zero) 4 4 2 lsb full-scale calibration error (with fixed 50 w resistor from ref out to ref in) (adjustable to zero) 0.25 0.25 0.125 % of fs temperature range C55 +125 C55 +125 C55 +125 c temperature coefficients (using internal reference) (t min to t max ) unipolar offset 2 (5) 1 (2.5) 1 (2.5) lsb (ppm/ c) bipolar offset 4 (10) 2 (5) 1 (2.5) lsb (ppm/ c) full-scale calibration 20 (50) 10 (25) 5 (12.5) lsb (ppm/ c) power supply rejection max change in full-scale calibration v cc = 15 v 1.5 v or 12 v 0.6 v 2 1 1 lsb v logic = 5 v 0.5 v 1/2 1/2 1/2 lsb v ee = C15 v 1.5 v or C12 v 0.6 v 2 1 1 lsb analog input input ranges bipolar C5 +5 C5 +5 C5 +5 volts C10 +10 C10 +10 C10 +10 volts unipolar 0 +10 0 +10 0 +10 volts 0 +20 0 +20 0 +20 volts input impedance 10 volt span 3 5 7 3 5 7 3 5 7 k w 20 volt span 6 10 14 6 10 14 6 10 14 k w digital characteristics 1 (t min Ct max ) inputs 2 (ce, cs , r/ c, a 0 ) logic 1 voltage +2.0 +5.5 +2.0 +5.5 +2.0 +5.5 volts logic 0 voltage C0.5 +0.8 C0.5 +0.8 C0.5 +0.8 volts current C20 +20 C20 +20 C20 +20 m a capacitance 5 5 5 pf output (db11Cdb0, sts) logic 1 voltage (i source 500 m a) +2.4 +2.4 +2.4 volts logic 0 voltage (i sink 1.6 ma) +0.4 +0.4 +0.4 volts leakage (db11Cdb0, high-z state) C20 +20 C20 +20 C20 +20 m a capacitance 5 5 5 pf power supplies operating range v logic +4.5 +5.5 +4.5 +5.5 +4.5 +5.5 volts v cc +11.4 +16.5 +11.4 +16.5 +11.4 +16.5 volts v ee C11.4 C16.5 C11.4 C16.5 C11.4 C16.5 volts operating current i logic 30 40 30 40 30 40 ma i cc 25 25 25 ma i ee 18 30 18 30 18 30 ma power dissipation 390 725 390 725 390 725 mw internal reference voltage 9.98 10.0 10.02 9.98 10.0 10.02 9.99 10.0 10.01 volts output current (available for external loads) 3 1.5 1.5 1.5 ma (external load should not change during conversion) package option 4 ceramic (d-28) ad574asd AD574ATD ad574aud notes 1 detailed timing specifications appear in the timing section. 2 12/ 8 input is not ttl-compatible and must be hard wired to v logic or digital common. 3 the reference should be buffered for operation on 12 v supplies. 4 d = ceramic dip. specifications subject to change without notice. ad574a rev. b C3C
ad574a rev. b C4C ordering guide resolution max temperature linearity error no missing codes full scale model 1 range max (t min to t max )(t min to t max ) t.c. (ppm/ c) ad574aj(x) 0 c to +70 c 1 lsb 11 bits 50.0 ad574ak(x) 0 c to +70 c 1/2 lsb 12 bits 27.0 ad574al(x) 0 c to +70 c 1/2 lsb 12 bits 10.0 ad574as(x) 2 C55 c to +125 c 1 lsb 11 bits 50.0 ad574at(x) 2 C55 c to +125 c 1 lsb 12 bits 25.0 ad574au(x) 2 C55 c to +125 c 1 lsb 12 bits 12.5 notes 1 x = package designator. available packages are: d (d-28) for all grades. e (e-28a) for j and k grades and /883b processed s, t and u grades. n (n-28) for j, k, and l grades. p (p-28a) for plcc in j, k grades. example: ad574akn is k grade in plastic dip. 2 for details on grade and package offerings screened in accordance with mil-std-883, refer to analog devices military products databook. 1 14 28 15 2 3 4 5 6 7 8 9 10 11 12 13 27 26 25 24 23 22 21 20 19 18 17 16 control clock sar 3 s t a t e o u t p u t b u f f e r s msb n i b b l e n i b b l e n i b b l e lsb 10v ref 12 12 c b a 12 ad574a 3k 19.95k 9.95k 5k 5k n dac v ee 8k i ref comp digital common dc i dac i dac = 4 x n x i ref +5v supply v logic data mode select 12/8 status sts db11 msb db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 lsb digital data outputs chip select cs byte address/ short cycle a o read/convert r/c chip enable ce +12/+15v supply v cc +10v reference ref out analog common ac reference input ref in -12/-15v supply v ee bipolar offset bip off 10v span input 10v in 20v span input 20v in ad574a block diagram and pin configuration absolute maximum ratings* (specifications apply to all grades, except where noted) v cc to digital common . . . . . . . . . . . . . . . . . . 0 v to +16.5 v v ee to digital common . . . . . . . . . . . . . . . . . . . 0 v to C16.5 v v logic to digital common . . . . . . . . . . . . . . . . . . 0 v to +7 v analog common to digital common . . . . . . . . . . . . . . . 1 v control inputs (ce, cs , a o 12/ 8 , r/ c ) to digital common . . . . . . . . . . . . . . C0.5 v to v logic + 0.5 v analog inputs (ref in, bip off, 10 v in ) to analog common . . . . . . . . . . . . . . . . . . . . . . . . . v ee to v cc 20 v in to analog common . . . . . . . . . . . . . . . . . . . . . . 24 v ref out . . . . . . . . . . . . . . . . . . indefinite short to common momentary short to v cc chip temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 c power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 825 mw lead temperature (soldering, 10 sec). . . . . . . . . . . . . +300 c storage temperature (ceramic) . . . . . . . . . . C65 c to +150 c (plastic) . . . . . . . . . . . . . . . . . . . . . . . . . . . C25 c to +100 c *stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ad574a rev. b C5C definitions of specifications linearity error linearity error refers to the deviation of each individual code from a line drawn from zero through full scale. the point used as zero occurs 1/2 lsb (1.22 mv for 10 volt span) be- fore the first code transition (all zeros to only the lsb on). full scale is defined as a level 1 1/2 lsb beyond the last code transition (to all ones). the deviation of a code from the true straight line is measured from the middle of each particular code. the ad574ak, l, t, and u grades are guaranteed for maxi- mum nonlinearity of 1/2 lsb. for these grades, this means that an analog value which falls exactly in the center of a given code width will result in the correct digital output code. values nearer the upper or lower transition of the code width may pro- duce the next upper or lower digital output code. the ad574aj and s grades are guaranteed to 1 lsb max error. for these grades, an analog value which falls within a given code width will result in either the correct code for that region or either adjacent one. note that the linearity error is not user-adjustable. differential linearity error (no missing codes) a specification which guarantees no missing codes requires that every code combination appear in a monotonic increasing se- quence as the analog input level is increased. thus every code must have a finite width. for the ad574ak, l, t, and u grades, which guarantee no missing codes to 12-bit resolution, all 4096 codes must be present over the entire operating tem- perature ranges. the ad574aj and s grades guarantee no miss- ing codes to 11-bit resolution over temperature; this means that all code combinations of the upper 11 bits must be present; in practice very few of the 12-bit codes are missing. unipolar offset the first transition should occur at a level 1/2 lsb above analog common. unipolar offset is defined as the deviation of the actual trans ition from that point. this offset can be adjusted as discussed on the following two pages. the unipolar offset temperature coefficient specifies the maximum change of the transition point over temperature, with or without external adjustment. bipolar offset in the bipolar mode the major carry transition (0111 1111 1111 to 1000 0000 0000) should occur for an analog value 1/2 lsb below analog common. the bipolar offset error and temperature coefficient specify the initial deviation and maximum change in the error over temperature. quantization uncertainty analog-to-digital converters exhibit an inherent quantization uncertainty of 1/2 lsb. this uncertainty is a fundamental characteristic of the quantization process and cannot be reduced for a converter of given resolution. left-justified data the data format used in the ad574a is left-justified. this means that the data represents the analog input as a fraction of full-scale, ranging from 0 to 4095 4096 . this implies a binary point to the left of the msb . full-scale calibration error the last transition (from 1111 1111 1110 to 1111 1111 1111) should occur for an analog value 1 1/2 lsb below the nominal full scale (9.9963 volts for 10.000 volts full scale). the full-scale calibration error is the deviation of the actual level at the last transition from the ideal level. this error, which is typically 0.05% to 0.1% of full scale, can be trimmed out as shown in figures 3 and 4. temperature coefficients the temperature coefficients for full-scale calibration, unipolar offset, and bipolar offset specify the maximum change from the initial (25 c) value to the value at t min or t max . power supply rejection the standard specifications for the ad574a assume use of +5.00 v and 15.00 v or 12.00 v supplies. the only effect of power supply error on the performance of the device will be a small change in the full-scale calibration. this will result in a linear change in all lower order codes. the specifications show the maximum full-scale change from the initial value with the supplies at the various limits. code width a fundamental quantity for a/d converter specifications is the code width. this is defined as the range of analog input values for which a given digital output code will occur. the nominal value of a code width is equivalent to 1 least significant bit (lsb) of the full-scale range or 2.44 mv out of 10 volts for a 12-bit adc. the ad574a offers guaranteed maximum linearity error over the full operating temperature range
ad574a rev. b C6C circuit operation the ad574a is a complete 12-bit a/d converter which requires no external components to provide the complete successive- approximation analog-to-digital conversion function. a block diagram of the ad574a is shown in figure 1. 1 14 28 15 2 3 4 5 6 7 8 9 10 11 12 13 27 26 25 24 23 22 21 20 19 18 17 16 control clock sar 3 s t a t e o u t p u t b u f f e r s msb n i b b l e n i b b l e n i b b l e lsb 10v ref 12 12 c b a 12 ad574a 3k 19.95k 9.95k 5k 5k n dac v ee 8k i ref comp digital common dc i dac i dac = 4 x n x i ref +5v supply v logic data mode select 12/8 status sts db11 msb db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 lsb digital data outputs chip select cs byte address/ short cycle a o read/convert r/c chip enable ce +12/+15v supply v cc +10v reference ref out analog common ac reference input ref in -12/-15v supply v ee bipolar offset bip off 10v span input 10v in 20v span input 20v in figure 1. block diagram of ad574a 12-bit a-to-d converter when the control section is commanded to initiate a conversion (as d escribed later), it enables the clock and resets the successive- approximation register (sar) to all zeros. once a conversion cycle has begun, it cannot be stopped or restarted and data is not available from the output buffers. the sar, timed by the clock, will sequence through the conversion cycle and return an end-of-convert flag to the control section. the control section will then disable the clock, bring the output status flag low, and enable control functions to allow data read functions by external command. during the conversion cycle, the internal 12-bit current output dac is sequenced by the sar from the most significant bit (msb) to least significant bit (lsb) to provide an output cur- rent which accurately balances the input signal current through the 5 k w (or 10 k w ) input resistor. the comparator determines whether the addition of each successively-weighted bit current causes the dac current sum to be greater or less than the input current; if the sum is less, the bit is left on; if more, the bit is turned off. after testing all the bits, the sar contains a 12-bit binary code which accurately represents the input signal to within 1/2 lsb. the temperature-compensated buried zener reference provides the primary voltage reference to the dac and guarantees excel- lent stability with both time and temperature. the reference is trimmed to 10.00 volts 0.2%; it can supply up to 1.5 ma to an external load in addition to the requirements of the reference in- put resistor (0.5 ma) and bipolar offset resistor (1 ma) when the ad574a is powered from 15 v supplies. if the ad574a is used with 12 v supplies, or if external current must be sup- plied over the full temperature range, an external buffer ampli- fier is recommended. any external load on the ad574a reference must remain constant during conversion. the thin-film application resistors are trimmed to match the full-scale output current of the dac. there are two 5 k w input scaling resistors to allow either a 10 volt or 20 volt span. the 10 k w bipolar offset resistor is grounded for unipolar operation and connected to the 10 volt reference for bipolar operation. driving the ad574 analog input the internal circuitry of the ad574 dictates that its analog input be driven by a low source impedance. voltage changes at the current summing node of the internal comparator result in abrupt modulations of the current at the analog input. for accu- rate 12-bit conversions the driving source must be capable of holding a constant output voltage under these dynamically changing load conditions. current output dac sar comparator ad574a i in i test r in i diff v+ v feedback to amplifier analog common i in is modulated by changes in test current. amplifier pulse load response limited by open loop output impedance. current limiting resistors figure 2. op amp C ad574a interface the output impedance of an op amp has an open-loop value which, in a closed loop, is divided by the loop gain available at the frequency of interest. the amplifier should have acceptable loop gain at 500 khz for use with the ad574a. to check whether the output properties of a signal source are suitable, monitor the ad574s input with an oscilloscope while a conver- sion is in progress. each of the 12 disturbances should subside in 1 m s or less. for applications involving the use of a sample-and-hold ampli- fier, the ad585 is recommended. the ad711 or ad544 op amps are recommended for dc applications. sample-and-hold amplifiers although the conversion time of the ad574a is a maximum of 35 m s, to achieve accurate 12-bit conversions of frequencies greater than a few hz requires the use of a sample-and-hold amplifier (sha). if the voltage of the analog input signal driving the ad574a changes by more than 1/2 lsb over the time interval needed to make a conversion, then the input requires a sha. the ad585 is a high linearity sha capable of directly driving the analog input of the ad574a. the ad585s fast acquisition time, low aperture and low aperture jitter are ideally suited for high-speed data acquisition systems. consider the ad574a converter with a 35 m s conversion time and an input signal of 10 v p-p: the maximum frequency which may be applied to achieve rated accuracy is 1.5 hz. however, with the addition of an ad585, as shown in figure 3, the maximum frequency increases to 26 khz. the ad585s low output impedance, fast-loop response, and low droop maintain 12-bits of accuracy under the changing load conditions that occur during a conversion, making it suitable for use in high accuracy conversion systems. many other shas cannot achieve 12-bits of accuracy and can thus compromise a system. the ad585 is recommended for ad574a applications requiring a sample and hold. an alternate approach is to use the ad1674, which combines the adc and sha on one chip, with a total throughput time of 10 m s.
ad574a rev. b C7C a 8 10 13 12 3 15 4 9 a2 ad574a 27 16 12-bit 3-state data + c3 c1 c2 + + +15v +5v ?5v +v s to a1 ? s to a1 14 13 12 11 10 9 8 1234567 a r4 100k +15v ?5v r1 100k offset r3 100w 7404 or eq. convert status gain r2 100w v ref agnd +v s ? s analog input 0v to +10v 10k 10k 100pf a1 ad585 17 6 2 11 note 1. c1, c2, c3 are 47 mf tantalum, bypassed by 0.1 mf ceramic. locate at associated a2 pins. m m 28 5 figure 3. ad574a with ad585 sample and hold supply decoupling and layout considerations it is critically important that the ad574a power supplies be fil- tered, well regulated, and free from high frequency noise. use of noisy supplies will cause unstable output codes. switching power supplies are not recommended for circuits attempting to achieve 12-bit accuracy unless great care is used in filtering any switching spikes present in the output. remember that a few millivolts of noise represents several counts of error in a 12-bit adc. decoupling capacitors should be used on all power supply pins; the +5 v supply decoupling capacitor should be connected directly from pin 1 to pin 15 (digital common) and the +v cc and Cv ee pins should be decoupled directly to analog common (pin 9). a suitable decoupling capacitor is a 4.7 m f tantalum type in parallel with a 0.1 m f disc ceramic type. circuit layout should attempt to locate the ad574a, associated analog input circuitry, and interconnections as far as possible from logic circuitry. for this reason, the use of wire-wrap circuit construction is not recommended. careful printed circuit con- struction is preferred. grounding considerations the analog common at pin 9 is the ground reference point for the internal reference and is thus the high quality ground for the ad574a; it should be connected directly to the analog refer- ence point of the system. in order to achieve all of the high accuracy performance available from the ad574a in an envi- ronment of high digital noise content, the analog and digital commons should be connected together at the package. in some situations, the digital common at pin 15 can be connected to the most convenient ground reference point; analog power return is preferred. unipolar range connections for the ad574a the ad574a contains all the active components required to perform a complete 12-bit a/d conversion. thus, for most situ- ations, all that is necessary is connection of the power supplies (+5 v, +12 v/+15 v and C12 v/C15 v), the analog input, and the conversion initiation command, as discussed on the next page. analog input connections and calibration are easily ac- complished; the unipolar operating mode is shown in figure 4. 9 14 13 12 8 10 6 5 4 3 2 28 15 11 7 1 27 24 19 16 23 20 ad574a sts high bit middle bits low bits +5v +15v ?5v dig com 12/8 cs a o r/c ce ref in ref out bip off 10v in 20v in ana com offset r1 100k ?2v/?5v +12v/+15v gain 100k r2 100w 100w analog inputs 0 to +10v 0 to +20v figure 4. unipolar input connections all of the thin-film application resistors of the ad574a are trimmed for absolute calibration. therefore, in many applica- tions, no calibration trimming will be required. the absolute accuracy for each grade is given in the specification tables. for example, if no trims are used, the ad574ak guarantees 1 lsb max zero offset error and 0.25% (10 lsb) max full-scale error. (typical full-scale error is 2 lsb.) if the offset trim is not required, pin 12 can be connected directly to pin 9; the two resistors and trimmer for pin 12 are then not needed. if the full-scale trim is not needed, a 50 w 1% metal film resistor should be connected between pin 8 and pin 10. the analog input is connected between pin 13 and pin 9 for a 0 v to +10 v input range, between 14 and pin 9 for a 0 v to +20 v input range. the ad574a easily accommodates an input signal beyond the supplies. for the 10 volt span input, the lsb has a nominal value of 2.44 mv; for the 20 volt span, 4.88 mv. if a 10.24 v range is desired (nominal 2.5 mv/bit), the gain trimmer (r2) should be replaced by a 50 w resistor, and a 200 w trimmer inserted in series with the analog input to pin 13 for a full-scale range of 20.48 v (5 mv/bit), use a 500 w trim- mer into pin 14. the gain trim described below is now done with these trimmers. the nominal input impedance into pin 13 is 5 k w , and 10 k w into pin 14. unipolar calibration the ad574a is intended to have a nominal 1/2 lsb offset so that the exact analog input for a given code will be in the middle of that code (halfway between the transitions to the codes above and below it). thus, the first transition (from 0000 0000 0000 to 0000 0000 0001) will occur for an input level of +1/2 lsb (1.22 mv for 10 v range). if pin 12 is connected to pin 9, the unit will behave in this man- ner, within specifications. if the offset trim (r1) is used, it should be trimmed as above, although a different offset can be set for a particular system requirement. this circuit will give ap- proximately 15 mv of offset trim range.
ad574a rev. b C8C the full-scale trim is done by applying a signal 1 1/2 lsb below the nominal full scale (9.9963 for a 10 v range). trim r2 to give the last transition (1111 1111 1110 to 1111 1111 1111). bipolar operation the connections for bipolar ranges are shown in figure 5. again, as for the unipolar ranges, if the offset and gain specifica- tions are sufficient, one or both of the trimmers shown can be replaced by a 50 w 1% fixed resistor. bipolar calibration is similar to unipolar calibration. first, a signal 1/2 lsb above negative full scale (C4.9988 v for the 5 v range) is applied and r1 is trimmed to give the first transition (0000 0000 0000 to 0000 0000 0001). then a signal 1 1/2 lsb below positive full scale (+4.9963 v the 5 v range) is applied and r2 trimmed to give the last transition (1111 11111110 to 1111 1111 1111). 9 14 13 12 8 10 6 5 4 3 2 28 15 11 7 1 27 24 19 16 23 20 ad574a sts high bit middle bits low bits +5v +15v ?5v dig com 12/8 cs a o r/c ce ref in ref out bip off 10v in 20v in ana com gain r2 100w analog inputs 65v r1 100w 610v offset figure 5. bipolar input connections control logic the ad574a contains on-chip logic to provide conversion ini- tiation and data read operations from signals commonly avail- able in microprocessor systems. figure 6 shows the internal logic circuitry of the ad574a. the control signals ce, cs , and r/ c control the operation of the converter. the state of r/ c when ce and cs are both asserted determines whether a data read (r/ c = 1) or a convert (r/ c = 0) is in progress. the register control inputs a o and 12/ 8 control conversion length and data format. the a o line is usually tied to the least significant bit of the address bus. if a conversion is started with a o low, a full 12-bit conversion cycle is initiated. if a o is high during a convert start, a shorter 8-bit conversion cycle results. during data read operations, a o deter- mines whether the three-state buffers containing the 8 msbs of the conversion result (a o = 0) or the 4 lsbs (a o = 1) are enabled. the 12/ 8 pin determines whether the output data is to be organized as two 8-bit words (12/ 8 tied to digital common) or a single 12-bit word (12/ 8 tied to v logic ). the 12/ 8 pin is not ttl-compatible and must be hard-wired to either v logic or digital common. in the 8-bit mode, the byte addressed when a o is high contains the 4 lsbs from the conversion followed by four trailing zeroes. this organization allows the data lines to be overlapped for direct interface to 8-bit buses without the need for external three-state buffers. it is not recommended that a o change state during a data read operation. asymmetrical enable and disable times of the three-state buffers could cause internal bus contention resulting in potential damage to the ad574a. read convert low if conversion in progress value of a0 at last convert command eoc8 eoc12 from note 1 nibble a, b, enable nibble c enable nibble b = o enable to output buffers start convert status r/c ce cs a0 12/8 (note 2) note 1: when start convert goes low, the eoc (end of conversion) signals go low. eoc8 returns high after an 8-bit conversion cycle is complete, and eoc12 returns high when all 12-bits have been converted. the eoc signals prevent data from being read during conversions. note 2: 12/8 is not a ttl-compatable input and should always be wired directly to v logic or digital common. figure 6. ad574a control logic an output signal, sts, indicates the status of the converter. sts goes high at the beginning of a conversion and returns low when the conversion cycle is complete. table i. ad574a truth table ce cs r/ c 12/ 8 a o operation 0 x x x x none x 1 x x x none 1 0 0 x 0 initiate 12-bit conversion 1 0 0 x 1 initiate 8-bit conversion 1 0 1 pin 1 x enable 12-bit parallel output 1 0 1 pin 15 0 enable 8 most significant bits 1 0 1 pin 15 1 enable 4 lsbs + 4 trailing zeroes timing the ad574a is easily interfaced to a wide variety of micropro- cessors and other digital systems. the following discussion of the timing requirements of the ad574a control signals should provide the system designer with useful insight into the opera- tion of the device. table ii. convert start timingfull control mode symbol parameter min typ max units t dsc sts delay from ce 400 ns t hec ce pulse width 300 ns t ssc cs to ce setup 300 ns t hsc cs low during ce high 200 ns t src r/ c to ce setup 250 ns t hrc r/ c low during ce high 200 ns t sac a o to ce setup 0 ns t hac a o valid during ce high 300 ns t c conversion time 8-bit cycle 10 24 m s 12-bit cycle 15 35 m s
ad574a rev. b C9C figure 7 shows a complete timing diagram for the ad574a con- vert start operation. r/ c should be low before both ce and cs are asserted; if r/ c is high, a read operation will momentarily occur, possibly resulting in system bus contention. either ce or cs may be used to initiate a conversion; however, use of ce is recommended since it includes one less propagation delay than cs and is the faster input. in figure 7, ce is used to initiate the conversion. figure 7. convert start timing once a conversion is started and the sts line goes high, convert start commands will be ignored until the conversion cycle is complete. the output data buffers cannot be enabled during conversion. figure 8 shows the timing for data read operations. during data read operations, access time is measured from the point where ce and r/ c both are high (assuming cs is already low). if cs is used to enable the device, access time is extended by 100 ns. figure 8. read cycle timing in the 8-bit bus interface mode (12/ 8 input wired to digital common), the address bit, a o , must be stable at least 150 ns prior to ce going high and must remain stable during the entire read cycle. if a o is allowed to change, damage to the ad574a output buffers may result. table iii. read timingfull control mode symbol parameter min typ max units t dd 1 access time (from ce) 200 ns t hd data valid after ce low 25 ns t hl 2 output float delay 100 ns t ssr cs to ce setup 150 ns t srr r/ c to ce setup 0 ns t sar a o to ce setup 150 ns t hsr cs valid after ce low 50 ns t hrr r/ c high after ce low 0 ns t har a o valid after ce low 50 ns notes 1 t dd is measured with the load circuit of figure 9 and defined as the time required for an output to cross 0.4 v or 2.4 v. 2 t hl is defined as the time required for the data lines to change 0.5 v when loaded with the circuit of figure 10. a. high-z to logic 1 b. high-z to logic 0 figure 9. load circuit for access time test a. logic 1 to high-z b. logic 0 to high-z figure 10. load circuit for output float delay test stand-alone operation the ad574a can be used in a stand-alone mode, which is useful in systems with dedicated input ports available and thus not requiring full bus interface capability. in this mode, ce and 12/ 8 are wired high, cs and a o are wired low, and conversion is controlled by r/ c . the three-state buff- ers are enabled when r/ c is high and a conversion starts when r/ c goes low. this allows two possible control signalsa high pulse or a low pulse. operation with a low pulse is shown in figure 11. in this case, the outputs are forced into the high impeda nce state in response to the falling edge of r/ c and return figure 11. low pulse for r/ c outputs enabled after conversion
ad574a rev. b C10C to valid logic levels after the conversion cycle is completed. the sts line goes high 600 ns after r/ c goes low and returns low 300 ns after data is valid. if conversion is initiated by a high pulse as shown in figure 12, the data lines are enabled during the time when r/ c is high. the falling edge of r/ c starts the next conversion, and the data lines return to three-state (and remain three-state) until the next high pulse of r/ c . figure 12. high pulse for r/ c outputs enabled while r/ c high, otherwise high-z table iv. stand-alone mode timing symbol parameter min typ max units t hrl low r/ c pulse width 250 ns t ds sts delay from r/ c 600 ns t hdr data valid after r/ c low 25 ns t hl output float delay 150 ns t hs sts delay after data valid 300 1000 ns t hrh high r/ c pulse width 300 ns t ddr data access time 250 ns usually the low pulse for r/ c stand-alone mode will be used. figure 13 illustrates a typical stand-alone configuration for 8086 type processors. the addition of the 74f/s374 latches improves bus access/release times and helps minimize digital feedthrough to the analog portion of the converter. figure 13. 8086 stand-alone configuration interfacing the ad574a to microprocessors the control logic of the ad574a makes direct connection to most microprocessor system buses possible. while it is impos- sible to describe the details of the interface connections for every microprocessor type, several representative examples will be described here. general a/d converter interface considerations a typical a/d converter interface routine involves several operations. first, a write to the adc address initiates a conver- sion. the processor must then wait for the conversion cycle to complete, since most adcs take longer than one instruction cycle to complete a conversion. valid data can, of course, only be read after the conversion is complete. the ad574a provides an output signal (sts) which indicates when a conversion is in progress. this signal can be polled by the processor by reading it through an external three-state buffer (or other input port). the sts signal can also be used to generate an interrupt upon completion of conversion, if the system timing requirements are critical (bear in mind that the maximum conversion time of the ad574a is only 35 microseconds) and the processor has other tasks to perform during the adc conversion cycle. another possible time-out method is to assume that the adc will take 35 microseconds to convert, and insert a sufficient number of do-nothing instructions to ensure that 35 microseconds of processor time is consumed. once it is established that the conversion is finished, the data can be read. in the case of an adc of 8-bit resolution (or less), a single data read operation is sufficient. in the case of convert- ers with more data bits than are available on the bus, a choice of data formats is required, and m ultiple read operations are needed. the ad574a includes internal logic to permit direct interface to 8-bit or 16-bit data buses, selected by connection of the 12/ 8 input. in 16-bit bus applications (12/ 8 high) the data lines (db11 through db0) may be connected to either the 12 most significant or 12 least significant bits of the data bus. the re- maining four bits should be masked in software. the interface to an 8-bit data bus (12/ 8 low) is done in a left-justified format. the even address (a0 low) contains the 8 msbs (db11 through db4). the odd address (a0 high) contains the 4 lsbs (db3 through db0) in the upper half of the byte, followed by four trailing zeroes, thus eliminating bit masking instructions. it is not possible to rearrange the ad574a data lines for right justified 8-bit bus interface. figure 14. ad574a data format for 8-bit bus specific processor interface examples z-80 system interface the ad574a may be interfaced to the z-80 processor in an i/o or memory mapped configuration. figure 15 illustrates an i/o or mapped configuration. the z-80 uses address lines a0Ca7 to decode the i/o port address. an interesting feature of the z-80 is that during i/o operations a single wait state is automatically inserted, allowing the ad574a to be used with z-80 processors having clock speeds up to 4 mhz. for applications faster than 4 mhz use the wait state generator in figure 16. in a memory mapped configuration the ad574a may be interfaced to z-80 processors with clock speeds of up to 2.5 mhz.
ad574a rev. b C11C figure 15. z80ad574a interface figure 16. wait state generator ibm pc interface the ad574a appears in figure 17 interfaced to the 4 mhz 8088 processor of an ibm pc. since the device resides in i/o space, its address is decoded from only the lower ten address lines and must be gated with aen (active low) to mask out in- ternal dma cycles which use the same i/o address space. this active low signal is applied to cs . ior and iow are used to initiate the conversion and read, and are gated together to drive the chip enable, ce. because the data bus width is limited to 8 bits, the ad574a data resides in two adjacent addresses selected by a0. figure 17. ibm pcad574a interface note: due to the large number of options that may be installed in the pc, the i/o bus loading should be limited to one schottky ttl load. therefore, a buffer/driver should be used when inter- facing more than two ad574as to the i/o bus. 8086 interface the data mode select pin (12/ 8 ) of the ad574a should be con- nected to v logic to provide a 12-bit data output. to prevent possible bus contention, a demultiplexed and buffered address/ data bus is recommended. in the cases where the 8-bit short conversion cycle is not used, a0 should be tied to digital com- mon. figure 18 shows a typical 8086 configuration. figure 18. 8086ad574a with buffered bus lnterface for clock speeds greater than 4 mhz wait state insertion similar to figure 16 is recommended to ensure sufficient ce and r/ c pulse duration. the ad574a can also be interfaced in a stand-alone mode (see figure 13). a low going pulse derived from the 8086s wr sig- nal logically ored with a low address decode starts the conver- sion. at the end of the conversion, sts clocks the data into the three-state latches. 68000 interface the ad574, when configured in the stand-alone mode, will eas- ily interf ace to the 4 mhz version of the 68000 microprocessor. the 68000 r/ w signal combined with a low address decode ini- tiates conversion. the uds or lds signal, with the decoded address, generates the dtack input to the processor, latching in the ad574as data. figure 19 illustrates this configuration. figure 19. 68000ad574a interface
ad574a rev. b C12C outline dimensions dimensions shown in inches and (mm). 28-pin ceramic dip package (d-28) 28-lead plastic dip package (n-28a) 28-terminal plcc package (p-28a) 4 pin 1 identifier 5 26 25 11 12 19 18 top view (pins down) 0.495 (12.57) 0.485 (12.32) sq 0.456 (11.58) 0.450 (11.43) sq 0.048 (1.21) 0.042 (1.07) 0.048 (1.21) 0.042 (1.07) 0.020 (0.50) r 0.050 (1.27) bsc 0.021 (0.53) 0.013 (0.33) 0.430 (10.92) 0.390 (9.91) 0.032 (0.81) 0.026 (0.66) 0.180 (4.57) 0.165 (4.19) 0.040 (1.01) 0.025 (0.64) 0.056 (1.42) 0.042 (1.07) 0.025 (0.63) 0.015 (0.38) 0.110 (2.79) 0.085 (2.16) 28Cterminal lcc package (e-28a) 0.075 (1.91) ref 0.075 (1.91) ref sq 0.458 (11.63) 0.442 (11.23) a a a a a a a a a a a a a a a a top view 0.088 (2.24) 0.054 (1.37) 0.100 (2.54) 0.064 (1.63) 0.458 (11.63) max sq 0.150 (3.81) bsc 0.011 (0.28) 0.007 (0.18) r typ bottom view 1 28 18 12 0.095 (2.41) 0.075 (1.90) 0.055 (1.40) 0.045 (1.14) 45 typ 0.200 (5.08) bsc 0.015 (0.38) min 0.028 (0.71) 0.022 (0.56) 0.050 (1.27) bsc 0.300 (7.62) bsc c704dC10C8/88 printed in u.s.a.

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